1. Field of the Invention
The present invention generally relates to semiconductor memory devices, and more particularly, to a timing scheme for semiconductor memory devices which enables, among other things, rapid data access during a read operation.
2. Background Information
Recent semiconductor technology has developed highly-integrated, large-capacity semiconductor memory devices. Semiconductor memory devices are comprised of many individual memory cells arranged in an array. Each memory cell is typically adapted to store one bit of digital data. In a memory array, groups of individual memory cells are arranged in columns with the individual cells in each column connected together by two conductors, often referred to as local bit lines. A memory array may include many columns of memory cells, with each column including a pair of local bit lines.
The local bit lines of a given column of memory cells are typically connected in some manner to another pair of bit lines, often referred to as global bit lines. Global bit lines typically operate in conjunction with many pairs of local bit lines to enable communication of data from many columns of memory cells with other components, such as processors and/or other memory devices. Accordingly, the use of local and global bit lines is hierarchical in nature, and a memory device using such lines may be referred to as a segmented memory device.
In addition to local and global bit lines, each memory cell in a memory array is typically connected to a conductor referred to as a word line. The memory array includes a number of word lines, each word line commonly connecting memory cells in a row across the different columns. The word lines are used to activate an individual cell in a particular column for a read operation from the cell, or a write operation to the cell. Accordingly, word lines, local bit lines, and global bit lines operate together to facilitate data transfer in a segmented memory device.
In order for a segmented memory device to perform optimally, the device should employ a timing scheme that enables small voltage differentials to be sensed on the local and global bit lines. In particular, such a timing scheme provides advantages such as high speed data access since less time is required for a minimum voltage differential to develop on the bit lines during a read operation. Moreover, power consumption for the device is reduced since smaller voltages can be used. Accordingly, there is a need for such a timing scheme for semiconductor memory devices. The present invention addresses these and other issues.
In accordance with principles of the present invention, a semiconductor memory device includes at least one memory cell for storing digital data. A local sense amplifier is operably coupled to the at least one memory cell for receiving a first signal representative of the digital data stored in the at least one memory cell, and outputting a second signal representative of the received first signal in response to a first strobe signal. A global sense amplifier is operably coupled to the local sense amplifier for receiving the second signal, and outputting a third signal representative of the received second signal in response to a second strobe signal. Dummy circuitry is provided for enabling generation of the first and second strobe signals.